This relates to integrated circuits with memory and, more particularly, to volatile memory elements.
Integrated circuits often contain volatile memory elements. A volatile memory element retains data only so long as the integrated circuit is powered. In the event of power loss, the data in the volatile memory element is lost. Although nonvolatile memory elements such as memory elements based on electrically-erasable programmable read-only memory technology are not subject to data loss in this way, it is often not desirable or possible to fabricate nonvolatile memory elements as part of a given integrated circuit.
As a result, volatile memory elements are often used. For example, static random-access memory (SRAM) chips contain SRAM cells, which are a type of volatile memory element. Volatile memory elements such as SRAM cells are typically based on cross-coupled inverters (latches). In each memory element, the cross-coupled inverters are connected to a data line via an address transistor that is turned on when data is being read from or written into the memory element. When no data is being read from or written into the memory element, the address transistor is turned off to isolate the memory element.
In conventional memory design, each data line is precharged prior to every read/write operation to help maximize memory performance. Even when the address transistor is turned off, however, leakage current can flow from the precharged data line through the deactivated address transistor. This is exacerbated as the size of address transistors are being increased to help improve read performance. Leakage generated in this way can account up to 70% or more of the total leakage in a memory array and consumes an excessive amount of power.
It is within this context that the embodiments described herein arise.